Production and Testing of the LHCb Outer Tracker Front End Readout Electronics

The LHCb Outer Tracker is a straw drift detector with a modular design and a total of 53760 readout channels distributed over a sensitive area of 12 double layers of 6x5 m each. The main electronics readout requirement is the precise ( 0.5 ns) drift time measurement at an occupancy of ∼4% and 1 MHz readout. A total of 128 channels are read out by one Front-End box. About half of the FE−Boxes have been built. Quality Assurance during the production has been performed on single FE−Box components. The assembled FE−Box is finally commissioned using a special FE-Tester. The FE−Tester is a programmable pulser with a time resolution of 150 ps capable to simulate all the functionality of the readout mimicking the real detector. Consequently, problems have been found and solved resulting in good overall performance. I. OVERVIEW OF THE READOUT SYSTEM The FE−Box readout has a modular structure consisting of four different type of boards: HV board (decoupling the analog signal from the high voltage), ASDBLR aboard (amplification), OTIS board (drift time measurement) and GOL auxiliary board (supply voltage and the optical link for data transmission). The boards are installed in an aluminum frame built to fit on the straw module providing the mechanical protection and electrical shielding to the electronics inside. The analog part of the electronics chain is the most critical and it will be treated with more emphasis. A. Amplifier Charge signals from the straw detector are decoupled from the high voltage and amplified, shaped and discriminated by the ATLAS ASDBLR chips. The main characteristics of the ASDBLR chip are: 1. Eight input channels and two test pulses (low and high). 2. A fast peaking time of ∼6ns due to a shaping network and the baseline restoration which separate the leading edge of the input signal and cut the ions induced current tail. 3. Radiation hardness withstanding 3.5 10 n/cm [1]. 4. Low cross talk of 0.2% and low noise of <1fC equivalent charge thanks to the DMILL bipolar process adopted for the chip production. 5. Optimized for grounding and heat dissipation through a 100 μm copper layer endowed in the PCB and several vias between the board layers. The block diagrams of the chip functionality is shown in Fig.1. Two ASDBLR chip are assembled on one ASDBLR board. Figure 1: Block diagram of the ASDBLR Chip. B. Time to Digital Converter (TDC) Digitized signal from two ASDBLR boards are then collected by the OTIS board [3] (Outer tracker Time Information System) which contains a 32 channel TDC. The chip is developed using a standard 0.25 μ CMOS process. The drift time data of each channel is stored in a pipeline of 4 μs waiting for the trigger veto. C. Gigabit Optical Link (GOL) At L0 accept the output of the TDC is collected by one Gigabit Optical Link chip (GOL) assembled in the GOL auxiliary board. The GOL board collects the signals coming from four OTIS boards and low voltage supply (+2.5 V and ± 3 V), TFC signals (Time and Fast Control) and IC slow control bus. Optical fibers carry the data ∼90 meters far from the detector at the L0 output rate of 1.1 MHz to the TELL1 board [2] in order to be filtered and finally stored for off-line processing. D. FE−Box The FE−Box consists of an aluminum chassis designed to fit one end of the detector module on which are installed 4 HV boards, 8 ASDBLR boards, 4 OTIS boards and 1 GOL auxiliary board. The FE−Chassis provides the cooling system, four inputs for the HV, the shielding cover and two connectors to fix the FE−Box on the straw module. In Fig.2 the drawing of as open FE−Box is shown. Figure 2: Outline of the FE−Box chassis with boards. II. FE−TEST SETUP DESCRIPTION The electronics readout requirements are a precise (∼0.5 ns) and efficient drift time measurement at an occupancy of 4% to ensure single hit resolution (200 micron) and efficient charged particle reconstruction. To achieve the desired performance, several steps of quality assurance during the production have been applied, using dedicated test setups for each type of board [7]. Figure 3: Block diagram of the FE Test Setup. The performance on an assembled FE−Box is verified through a final test performed using a special FE−Tester. The block diagram of the setup is shown in Fig.3. The FE−Tester is based on the test setup build for the Alice Alcapone tester. The heart of the setup is a PCB with an Altera programmable logic chip. Most of the electronics needed for the tests is built on the controller board. To interface the FE−Box a specific connection board is developed (Flipper Box) with the additional required electronics to provide the input signal on the 128 channels of the FE−Box. The logic in the Altera chip is controlled by a LabView program on a PC. The connection between them is a JTAG interface through the parallel port. For the communication with the FE−Box the I2C bus is used. The out-coming data stream from the GOL board is collected by the HOLA acquisition board [4]. The data exchange between the two machine and a file-server is guarantee by standard TCP. In summary the FE−Tester consists of a programmable pulser capable to provide all the functionality of the readout (slow and fast controls) mimicking the input signals as real module detector. the FE−Test functionality are here summarized: 1. Generation of input signals straw-like. Those signals are tunable in intensity and in time with a resolution of ∼0.5 fC and 150 ps respectively. 2. Generation TFT (Time and Fast Control). 3. Generation of I2C (Slow Control). 4. Power supply and data acquisition. All those operations are automatized and controlled through LabView. III. TEST OF THE FE−BOX The following tests have been performed on assembled FE−Boxes: 1. Threshold Characteristics. A threshold scan is done and the measurement of the half-efficiency-point is carried out for a fixed input charge. The relative variation of the halfefficiency-point is expected to be less than 60 mV (rougly corresponding to half fC) out of the 128 channels as required in the ASDBLR chip selection [6]. A threshold scan is also performed using the test pulse signals (low and high) generated in the ASDBLR chip. The last test on the preamplifier is done through an amplitude scan with fixed threshold to carry out the half-efficiency-point and the ENC (equivalent noise charge). 2. Timing. Measurement of the time conversion linearity and the channel-by-channel resolution of the OTIS board. 3. Noise. Dark noise is studied as function of the threshold. 4. Synchronization. Four 8 bit TDC chips are inside a single FE−Box. The time difference between test pulse and the L0 is checked with a latency scan and therefore the synchronization between channels is verified. A. Threshold Characteristics One general requirement of the preamplifier, is the channelby-channel uniformity response for the same input charge Qi. The efficiency, noise and occupancy are strongly sensitive to the threshold which influence the detector performance. The threshold must be chosen such that the uniformity between channels is guaranteed in a wide range of input charge. Given the function g(Qi) representing the signal amplitude after pre-amplification of the input charge Qi, to measure channelby-channel uniformity we need to ”compare” those amplitudes between channels defining an appropriate amplitude estimator. The easiest number to measure is the hit-efficiency. Varying the threshold from low to high, the hit-efficiency goes from 1 to 0. In the ideal condition of absence of noise the hit-efficiency profile against threshold would be modeled as a step function. Assuming Gaussian noise the expression for the hit-probability for a fixed threshold and input charge is [5]: Pr(Vthr , Qi) = N ∫ +∞